(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit device improving resistance to destruction caused by electrostatic discharge (ESD) between a digital circuit and an analog circuit in a semiconductor integrated circuit composed of multiple power supplies.
(b) Description of the Related Art
In recent years, semiconductor integrated circuits have been developed to integrate a digital circuit and an analog circuit on a single semiconductor chip as LSI chip technology progresses. In this kind of LSI chip in which the digital circuit and the analog circuit are combined, the influence of noises given by the digital circuit to the analog circuit is reduced by externally supplying plural power sources to each circuit. In order to avoid the destruction caused by ESD of the LSI chip, instead of complete separation between a power supply for the digital circuit and a power supply for the analog circuit and between a ground for the digital circuit and a ground for the analog circuit, the semiconductor integrated circuits are constructed so as to connect the digital circuit to the analog circuit via a circuit (hereinafter, referred to as a “protection circuit”) for avoiding destruction caused by ESD.
FIG. 11 is a diagram showing an exemplary structure of a known semiconductor integrated circuit 1000.
The semiconductor integrated circuit 1000 shown in FIG. 11 includes a digital circuit 1010 and an analog circuit 1050. The digital circuit 1010 and the analog circuit 1050 are connected via a control signal line 1080 to each other.
The digital circuit 1010 receives electrical signals from pads 1020a and 1020b through protection circuits 1022a and 1022b. A power supply pad 1024 supplies a digital power source 1034 to the protection circuits 1022a and 1022b. A power supply pad 1025 supplies a digital ground source 1035 to the protection circuits 1022a and 1022b. 
Likewise, the analog circuit 1050 receives electrical signals from pads 1060a and 1060b through the protection circuits 1062a and 1062b. A power supply pad 1064 supplies an analog power source 1074 to the protection circuits 1062a and 1062b. A power supply pad 1065 supplies an analog ground source 1075 to the protection circuits 1062a and 1062b. 
FIG. 12 is a diagram showing an exemplary structure of the protection circuits 1022a, 1022b, 1062a, and 1062b. For example, as shown in FIG. 12, each circuit is constructed using diodes so as to absorb a surge voltage. Thereby, even when surge voltages are mixed between the power supply pad 1024 for supplying a power source to the digital circuit 1010 and each of the pads 1020a and 1020b for inputting electrical signals, between the power supply pad 1025 and each of pads 1020a and 1020b, between the power supply pad 1064 for likewise supplying a power source to the analog circuit 1050 and each of the pads 1060a and 1060b for inputting electrical signals, and further between the power supply pad 1065 and each of the pads 1060a and 1060b, respectively, charges are bypassed by the circuit shown in FIG. 12, thereby avoiding destruction caused by ESD of the digital circuit 1010 and the analog circuit 1050.
As described above, the protection circuits 1022a and 1022b and the protection circuits 1062a and 1062b function only for the corresponding digital circuit 1010 and analog circuit 1050. In consideration of the case where charges are bypassed by the respective protection circuits 1022a, 1022b, 1062a, and 1062b, leading to the destruction caused by ESD between the digital circuit 1010 and the analog circuit 1050, a protection circuit 1090 is connected between the digital circuit 1010 and the analog circuit 1050. That is, a power source 1034 for the digital circuit 1010 and a power source 1074 for the analog circuit 1050 are connected via the protection circuit 1090 to each other, and ground sources 1035 and 1075 are done likewise.
FIG. 13 is a diagram showing an exemplary structure of the protection circuit 1090. For example, as shown in FIG. 13, the circuit is constructed using diodes so as to prevent the destruction caused by ESD from being caused between the digital circuit 1010 and the analog circuit 1050. The protection circuit 1090 prevents the digital circuit 1010 and the analog circuit 1050 from being directly connected to each other so that it also has the function of absorbing noises from the digital circuit 1010 to the analog circuit 1050.
Many protection circuits other than those having the structures shown in FIGS. 12 and 13 have been devised (for example, see Japanese Unexamined Patent Publications No. 10-56138 and 11-27404).
FIG. 14 is a diagram showing an example of a connection relationship between the pad in the semiconductor integrated circuit 1000 shown in FIG. 11 and a terminal of a package substrate.
For example, the pad 1025 in the semiconductor integrated circuit 1000 is electrically connected via a lead 1327 to a terminal 1326 located on a package substrate 1300 shown in FIG. 14. The connections of the other pads are also performed likewise.
FIG. 15 is a diagram showing an example of connection relationships between the terminals of the package substrate 1300 and external pins. As shown in FIG. 15, the terminal 1326 is electrically connected via an interconnect 1427 to an external pin 1426 inside the package substrate 1300. The connections of the other terminals are also performed likewise.
In this way, the package substrate 1300 and the semiconductor integrated circuit 1000 are connected to each other, and thereafter they are packaged by resin 1410 or the like so as to form an LSI chip 1400.
FIG. 16 is a flow chart showing process steps for fabricating the LSI chip 1400.
As shown in FIG. 16, the semiconductor integrated circuit 1000 is designed in step ST2000, and thereafter the process proceeds to step ST2010 to fabricate the semiconductor integrated circuit 1000. Next, the process proceeds to step ST2020 to integrate the semiconductor integrated circuit 1000 and the package circuit 1300, thereby forming the LSI chip 1400.
Thereafter, the process proceeds to step ST2100 for carrying out an LSI test for the LSI chip 1400. That is, step ST2100 for carrying out the LSI test includes at least step ST2110 for testing whether or not the digital circuit 1010 and the analog circuit 1050 satisfy the specification and step ST2120 for testing these circuits for destruction caused by ESD. After the LSI test in step ST2100, if it is found that the digital circuit 1010 and the analog circuit 1050 satisfy the specification and no destruction caused by ESD occurs, then it follows that the LSI chip 1400 has been completed. On the other hand, if it is found that the digital circuit 1010 or the analog circuit 1050 does not satisfy the specification or that the destruction caused by ESD occurs in the digital circuit 1010 or the analog circuit 1050, the process returns to the step ST2000 and repeats the subsequent steps.
However, as described above, the protection circuit 1090 is inserted for the purpose of reducing the influence of noises produced in the digital circuit 1010 and improving resistance to the ESD. However, when the period during which surge charges pass through the protection circuit 1090 is long, surge voltages may not be appropriately discharged. At this time, a high voltage may be applied, via a control signal that flows into a control signal line 1080 connecting the digital circuit 1010 to the analog circuit 1050, to these circuits, and thus a portion of the digital circuit 1010 or the analog circuit 1050 connecting the control signal line 1080 therebetween may be destroyed.
Such a case can be handled by changing the protection circuit 1090 in its design so as to reduce the period during which the surge charges pass through the protection circuit 1090. More particularly, it can be handled by again carrying out step ST2000 shown in FIG. 16. However, the semiconductor integrated circuit 1000 need again be fabricated as shown in step ST2010 shown in FIG. 16. The semiconductor integrated circuit 1000 is fabricated through multiple fabrication process steps. Therefore, a long period exceeding at least one month becomes necessary for again fabricating the semiconductor integrated circuit 1000. In addition, a mask required for fabrication costs very expensive. Besides, finally, the resistance to surge voltages applied to the LSI chip 1400 and the influence of noises need totally be judged. It is difficult to change the design of the protection circuit 1090 in view of all the conditions at the change of the design. Therefore, at the change of the design, it cannot surely be judged that the resistance to the ESD is improved and the influence of noises is also small.
This kind of destruction caused by ESD occurs with a high frequency in the process of carrying the LSI chip or the process of mounting the LSI chip to the substrate.